Gate-Level Leakage Characterization in Ultra- Low Power CMOS Circuits Using Time- Resolved Simulation Frameworks

Leakage power is a major issue in ultra-low-power CMOS circuits because static current becomes significant at low voltage and near-threshold operation. Although earlier studies examined leakage reduction and low-power gate behavior, they do not provide a unified time-resolved framework for comparing leakage across CMOS gate types and operating conditions. This article develops such a framework and studies the effects of switching, supply voltage, temperature, and delay-leakage tradeoff in representative CMOS gates. The results show that leakage is dynamic, gate-dependent, and mainly dominated by subthreshold conduction, while temperature and structural complexity further increase leakage sensitivity. The study concludes that low-power CMOS evaluation should consider temporal leakage behavior, thermal response, and timing cost together. These findings are useful for wearable electronics, always-on sensing systems, and other energy-constrained CMOS applications.